With development of microfabrication of a transistor, a transistor breakdown voltage is reduced. Accordingly, a power supply voltage of a semiconductor device tends to be reduced. The power supply voltage may also be reduced so as to reduce power consumption of the semiconductor device. In such a case, a threshold value of an MOS transistor used in the semiconductor device needs to be reduced so as to operate the semiconductor device at a high speed and a low power supply voltage. However, reduction of the threshold voltage of the transistor causes a problem of subthreshold current when the transistor is turned off. It has been traditionally considered that, when a clock for a CMOS semiconductor integrated circuit is stopped, consumption current does not flow. However, when the subthreshold current flows, the consumption current flows even if the clock is stopped. In order to cope with this problem, a power gating technology has been extensively used as a technology of reducing subthreshold current especially at a time of standby in which a clock is stopped. In the power gating technology, supply of a power supply to an internal circuit is shut off in a state where an output node potential needed to be held at the time of standby is kept constant.
Patent Document 1 describes a semiconductor device that uses a conventional power gating technology. FIG. 10 is a circuit block diagram showing a configuration of a conventional power gating circuit described in Patent Document 1. The conventional power gating circuit in FIG. 10 comprises a main power supply line MVL connected to a power supply Vdd, a sub power supply line SVL, and a P-channel MOS transistor QHP with a source thereof connected to the main power supply line MVL, a drain thereof connected to the sub power supply line SVL, and a gate thereof connected to a control signal/SCRC. This P-channel MOS transistor QHP functions as a power supply switch which is controlled to turn on/off by the control signal/SCRC. When the P-channel MOS transistor QHP turns on, the sub power supply line SVL is connected to the main power supply line MVL through this power supply switch. A transistor having a large absolute threshold voltage value is employed for the P-channel MOS transistor QHP which functions as this power supply switch in order to reduce subthreshold leak current when the P-channel MOS transistor QHP turns off.
The conventional power gating circuit in FIG. 10 further comprises a main ground line MGL connected to a ground Vss, a sub ground line SGL, and an N-channel MOS transistor QHN with a source thereof connected to the main ground line MGL, a drain thereof connected to the sub ground line SGL, and a gate thereof connected to a control signal SCRC. This N-channel MOS transistor QHN functions as a power supply switch which is controlled to turn on/off by the control signal SCRC. When the N-channel MOS transistor QHN turns on, the sub power supply line SGL is connected to the main power supply line MGL through this power supply switch. A transistor having a large absolute threshold voltage value is employed for the N-channel MOS transistor QHN which functions as this power supply switch in order to reduce subthreshold leak current when the N-channel MOS transistor QHN turns off.
The control signal SCRC and the control signal /SCRC are complementary signals. When the control signal SCRC goes high and the control signal /SCRC goes low, the power supply switches turn on. When the control signal SCRC goes low and the control signal /SCRC goes high, the power supply switches shut off. The control signal SCRC and the control signal /SCRC perform control so that the power supply switches shut off in a standby state and the power supply switches turn on when the standby state is released.
Further, internal circuits 104 and 106 are connected to the sub power supply line SVL and the sub power supply line SGL. The internal circuits are so controlled that, when the power supply switches turn on, a power supply is supplied to the internal circuits through the power supply switches, and when the power supply switches shut off, the supply of the power supply is stopped to cause subthreshold current not to flow.
For the semiconductor device in Patent Document 1, an inter-power supply capacitor cell 102 is further provided. The inter-power supply capacitor cell 102 includes a capacitor SC connected between the sub power supply line SVL and the sub ground line SGL, a capacitor VDC connected between the main power supply line MVL and the sub ground line SGL, and a capacitor VSC connected between the sub power supply line SVL and the main ground line MGL. Patent Document 1 describes that this inter-power supply capacitor cell 102 can reduce a voltage drop in each sub power supply line at the time of consumption of current, thereby allowing stabilization of operation of each internal circuit and improvement of an operation speed of each internal circuit.    [Patent Document 1]    JP Patent Kokai Publication No. JP-P-2000-195254A, which corresponds to US Publication No. US2002/000873A1 and U.S. Pat. No. 6,384,674B2.